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Si4355
3. Functional Description
SDN
GPIO3
Rx Chain
Synthesizer
GPIO2
XIN XOUT
25-32MHz XO
nSEL
RXp
LNA
PGA
ADC
Rx Modem
SDI
SDO
RXn
Battery
SCLK
nIRQ
VDD
Voltage
Sensor
Aux ADC
GPIO0
GPIO1
Figure 2. Si4355 Functional Block Diagram
3.1. Overview
The Si4355 is an easy-to-use, size efficient, low current wireless ISM receiver that covers the sub-GHz bands. The
wide operating voltage range of 1.8–3.6 V and low current consumption make the Si4355 an ideal solution for
battery powered applications. The Si4355 uses a single-conversion mixer to downconvert the FSK/GFSK or OOK
modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is
converted to the digital domain by a high performance ?? ADC allowing filtering, demodulation, slicing, and packet
handling to be performed in the built-in DSP, increasing the receiver ’s performance and flexibility versus analog
based architectures. The demodulated signal is output to the system MCU through a programmable GPIO or via
the standard SPI bus by reading the 64-byte Rx FIFO.
A high precision local oscillator (LO) is used and is generated by an integrated VCO and ?? Fractional-N PLL
synthesizer. The Si4355 operates in the frequency bands of 283–350, 425–525, and 850–960 MHz.
Additional system features, such as 64 byte Rx FIFO, preamble detection, sync word detector and CRC, reduce
overall current consumption, and allow for the use of lower-cost system MCUs. Power-on-reset (POR), and GPIOs
further reduce overall system cost and size. The Si4355 is designed to work with an MCU, crystal, and a few
passives to create a very compact and low-cost system.
3.2. Receiver Chain
The internal low-noise amplifier (LNA) is designed to be a wide-band LNA that can be matched with three external
discrete components to cover any common range of frequencies in the sub-GHz band. The LNA has extremely low
noise to suppress the noise of the following stages and achieve optimal sensitivity; so, no external gain or front-end
modules are necessary. The LNA has gain control, which is controlled by the internal automatic gain control (AGC)
algorithm. The LNA is followed by an I-Q mixer, filter, programmable gain amplifier (PGA), and ADC. The I-Q
mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic
range of the ADC. The ADC rejects out-of-band blockers and converts the signal to the digital domain where
filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and
PGA for use in the AGC algorithm.
Rev 1.0
11
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